HookThe 1945 report that fixed the shape of every computer since
In June 1945 the mathematician John von Neumann circulated a document titled the First Draft of a Report on the EDVAC. It was thirty years of computing distilled into one idea: a machine should hold its program instructions in the same memory as its data, so that a computer could be reprogrammed by loading new instructions rather than rewired by hand — which is exactly how the ENIAC before it had been 'programmed', by women moving cables for days. That single decision is why the laptop you are reading this on can be a word processor one minute and a game the next. The layout he described — a processor, a single main memory holding instructions and data, and buses connecting them — is called the von Neumann architecture, and it is still the shape of the chip in your phone.
This section is that machine, opened up. You will meet the components inside the box and the three buses that wire them together; the registers the processor uses as its own tiny scratchpad; the Fetch-Execute cycle that is the heartbeat of every program; the instruction set and addressing modes that decide what a single machine instruction can say; interrupts, which let a slow keyboard grab a fast processor's attention; the handful of factors that make one chip faster than another; and the input, output and secondary storage devices around the edge. The examiner's favourite move is to make you trace a real instruction through real registers, so treat the Fetch-Execute cycle as the load-bearing wall of the whole topic.
ModelInside the box: components, buses and the stored program
A von Neumann computer has four parts you must be able to name: the processor (the CPU, which fetches and executes instructions), main memory (RAM, holding both the instructions and the data of the running program), input/output controllers (which manage devices), and the buses that carry signals between them. A bus is simply a set of parallel wires shared by the components, and the specification names three. The address bus carries the address of the memory location the processor wants to read or write; it is unidirectional (address only ever flows out of the processor) and its width is decisive — an address bus of n lines can specify 2 to the power n distinct locations. The data bus carries the actual data or instruction to or from that location and is bidirectional. The control bus carries timing and command signals such as 'read', 'write', 'clock' and 'interrupt request', coordinating everything else.
The stored program concept is the principle underneath all of this: machine-code instructions are stored in main memory, in binary, indistinguishable in form from the data they operate on, and are fetched and executed in sequence. Because instructions are just numbers in memory, a program can be loaded, replaced or even (in principle) modified like any other data — which is what makes a general-purpose computer general-purpose. The price is the von Neumann bottleneck: instructions and data share one memory and one path to it, so the processor can spend time waiting on that single channel, which is why real chips bolt on cache to relieve it.
ModelThe processor and its registers
Open the processor and you find three working parts plus a set of registers. The Arithmetic Logic Unit (ALU) performs the calculations and logical comparisons. The Control Unit (CU) decodes each instruction and sends the control signals that make the rest of the machine obey it. The clock generates a regular pulse that synchronises every step. A register is a very small, very fast store inside the processor itself, and the A-level expects you to know the dedicated ones by role. The Program Counter (PC) holds the address of the next instruction to fetch. The Current Instruction Register (CIR) holds the instruction currently being decoded and executed. The Memory Address Register (MAR) holds the address of the location about to be accessed. The Memory Buffer Register (MBR), also called the Memory Data Register, holds the data or instruction just read from, or about to be written to, memory. The Accumulator (ACC) holds the result of ALU operations. A Status Register holds condition flags such as zero, negative and carry.
The key mental model is that the processor never operates on memory directly: it copies a value into a register, works on it there, and writes it back. Registers exist because they are far faster to access than main memory, so the whole design of the Fetch-Execute cycle is a choreography of moving values between these named registers at exactly the right moments.
MechanismThe Fetch-Execute cycle: the heartbeat
Every instruction a computer runs goes through the same three phases: fetch, decode, execute. In the fetch phase the address in the PC is copied to the MAR; the processor reads the location at that address over the buses and the instruction arrives in the MBR; the PC is incremented so it already points at the next instruction; and the fetched instruction is copied from the MBR into the CIR. In the decode phase the Control Unit interprets the bit pattern in the CIR, splitting it into an opcode (what to do) and an operand (what to do it to). In the execute phase the instruction is carried out — the ALU adds, a value is loaded or stored, or the PC is overwritten to jump — after which the cycle repeats. Writing the cycle as register transfers is what earns the marks: state which register's contents move where at each step.
Trace the very first fetch of a program whose instruction at address 0 is MOV R0, #5 and where the PC starts at 0.
Fetch: PC (=0) is copied to MAR, so MAR = 0. The control bus signals a read; main memory returns the instruction at location 0 down the data bus into the MBR. The PC is incremented to 1. The instruction is copied from MBR to CIR. Decode: the CU reads CIR, recognises the opcode as MOV and the operand as the immediate value 5. Execute: the value 5 is written into register R0. The cycle then restarts with PC = 1, ready to fetch the next instruction. Notice the PC was incremented during the fetch, before the instruction even executed — that is why a jump instruction has to overwrite the PC in its execute phase to change the flow, and it is the detail candidates most often leave out.
ModelInstruction set, addressing modes and assembly
The instruction set is the complete list of machine-code operations a particular processor understands — arithmetic (ADD, SUB), data movement (LDR, STR, MOV), comparison and branching (CMP, B, BEQ), and logic (AND, ORR, EOR). Each machine instruction is a binary pattern of an opcode and one or more operands; assembly language is the human-readable version, using mnemonics with a broadly one-to-one mapping to machine code. The subtlety the exam tests is the addressing mode — how the operand should be interpreted. In immediate addressing the operand is the value to use (written with a # in the AQA notation, e.g. MOV R0, #5 puts the literal 5 into R0). In direct addressing the operand is a memory address, and the value to use is whatever is stored there (e.g. LDR R1, 100 loads the contents of location 100, not the number 100). Confusing the two is the single most common assembly error.
The payoff of direct addressing is indirection: because the operand names a location, the same instruction fetches whatever currently lives there, which is how variables work. Immediate addressing is faster (no memory access) but the value is fixed at write-time.
Follow this five-line program. Assume memory location 100 already holds the value 3.
MOV R0, #5 — immediate: put the literal 5 into R0, so R0 = 5. LDR R1, 100 — direct: load the contents of location 100 into R1, so R1 = 3 (not 100). ADD R2, R0, R1 — R2 = R0 + R1 = 5 + 3 = 8. STR R2, 101 — direct: store the value in R2 into memory location 101, so location 101 now holds 8. HALT — stop. The two loads look almost identical on the page, yet one moved the number 5 and the other moved the number 3 that happened to live at address 100 — reading '#' as 'the value itself' and a bare number as 'the address of the value' is exactly the distinction the mark scheme rewards.
MechanismInterrupts: how a slow device grabs a fast processor
A processor running at billions of cycles a second cannot afford to sit in a loop asking a keyboard 'anything yet?' millions of times. Instead the device raises an interrupt — a signal on the control bus that says 'I need attention'. At the end of each Fetch-Execute cycle the processor checks for pending interrupts. If one is present and its priority is higher than the task currently running, the processor saves its state — the current register contents, crucially the PC — by pushing them onto the stack, then loads the address of the appropriate Interrupt Service Routine (ISR) from an interrupt vector table and runs it. When the ISR finishes, the saved state is popped off the stack and the interrupted program resumes exactly where it left off, unaware it was ever paused.
Priorities matter because interrupts can themselves be interrupted: a power-failure warning outranks a print-buffer-empty signal, so a low-priority ISR can be suspended for a high-priority one. Typical sources are input/output completion, timers, hardware faults and power failure. The examinable insight is that interrupts make the machine responsive and efficient: the processor does useful work until the instant a device actually needs it, rather than wasting cycles polling.
DataFactors affecting processor performance
Several independent factors decide how fast a processor gets through work, and a good answer weighs them rather than naming just one. Clock speed, measured in hertz, is the number of cycles per second; a 3.5 GHz clock ticks 3.5 billion times a second, and more instructions per second generally means more work — but only if the rest of the machine can keep up. Number of cores: a multi-core processor has several complete processing units and can genuinely execute several instructions at once, but performance does not simply double with two cores, because many problems cannot be split into independent parts and some code must run sequentially. Cache is a small, very fast memory on or near the processor that holds recently and frequently used instructions and data; more cache, and faster levels (L1, then L2, then L3), mean fewer slow trips to main memory and directly relieve the von Neumann bottleneck. Word length and bus width set how many bits move or are processed at once — a wider data bus shifts more per cycle, and a wider address bus can address more memory.
A calculation the exam loves. A processor has a 32-bit address bus. How much memory can it directly address? Each address line is one bit, so the number of distinct addresses is 2 to the power 32 = 4,294,967,296 locations. If each location stores one byte, that is 4,294,967,296 bytes = 4 GiB — which is exactly why 32-bit operating systems hit a ~4 GB memory ceiling and why 64-bit machines (a 2 to the power 64 address space) exist. Second calculation: two processors, one at 4 GHz single-core and one at 2 GHz quad-core. The quad-core has more total cycles per second (4 x 2 = 8 billion versus 4 billion), so it wins on tasks that parallelise well, such as video rendering; but on a single-threaded task that cannot be split, the 4 GHz core finishes first. Stating that dependency is what turns a list of facts into an evaluative answer.
ModelInput, output and secondary storage
A computer needs a way to get data in and results out, handled by input and output devices managed through I/O controllers. Input devices convert a real-world signal into data: a barcode reader shines a light and measures the reflected pattern of light and dark bars; a digital camera focuses light onto a grid of light-sensitive sensors that produce a number per pixel; an RFID reader energises a nearby tag wirelessly and reads back its stored ID. Output devices do the reverse: a laser printer uses a laser to draw a charged image on a drum that attracts toner and fuses it to paper.
Secondary storage is needed because main memory is volatile (it loses its contents when powered off) and comparatively small and expensive; secondary storage is non-volatile, larger and cheaper per gigabyte, and holds programs and files between sessions. The three technologies to contrast are magnetic (a hard disk drive stores bits as magnetised regions on spinning platters read by a moving head — high capacity, low cost, but mechanical and slower), optical (CD, DVD and Blu-ray store bits as pits and lands on a disc read by a laser — cheap and portable, low capacity), and solid state (an SSD or flash drive stores bits as charge in NAND flash memory cells with no moving parts — fast, robust and low-power, but historically dearer per gigabyte). Match the technology to the need: an SSD for a fast boot drive, a magnetic HDD for cheap bulk backup, optical for distributing read-only media.
VocabularyKey terms the mark scheme pays for
TrapsMisconceptions that cost marks
ExamWhat examiners want
Computer organisation is assessed on the written Paper 2 (7517/2), and the marks are unusually predictable, so bank them. For Fetch-Execute questions, answer in register transfers: name which register's contents move where at each step (PC to MAR, memory to MBR, PC incremented, MBR to CIR), because a mark is typically awarded per correct transfer and a vague prose summary earns few of them. When an assembly or addressing-mode question appears, read every operand carefully and state explicitly whether it is immediate (the value) or direct (the address of the value) — the whole answer usually turns on that one distinction.
Match the response to the assessment objective. AO1 'state/describe' questions want precise definitions and correct roles — the MAR holds an address, the MBR holds data, the ALU calculates, the CU decodes — so keep them crisply separate. AO2 'explain/justify/compare' questions almost always hinge on a trade-off: more cores help only parallelisable tasks, higher clock speed helps only if cache keeps the processor fed, an SSD beats an HDD on speed but historically not on cost per gigabyte. Never answer these with a single factor; name the competing considerations and tie your judgement to the scenario given. For interrupt questions, structure the answer around save-state-to-stack, run the ISR, restore-state, and mention priorities, because that sequence is the reward pattern examiners look for.